A synthesis method to propagate false path information from RTL to gate level

This paper proposes a new synthesis method for propagating information of paths from register transfer level (RTL) to gate level. The method enables false path identification at RTL without not only enforcing strong constraints on logic synthesis but also loss of the information about false paths identified. Experiments show that the proposed method can reduce hardware and timing overhead and improve propagability of false path information through logic synthesis compared with the previous methods.