DocumentCode
2742791
Title
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects
Author
Iizuka, Tetsyta ; Nakura, Toru ; Asada, Kunihiro
Author_Institution
VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan
fYear
2010
fDate
14-16 April 2010
Firstpage
167
Lastpage
172
Abstract
In this paper, we propose an all-digital process variability and aging monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. The experimental results of the circuit simulation on 65 nm CMOS process indicate the feasibility of the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the infield monitoring of aging effects such as negative bias instability (NBTI) and channel hot carrier (CHC).
Keywords
CMOS integrated circuits; buffer circuits; circuit simulation; monitoring; oscillators; CMOS process; NMOS devices; PMOS devices; aging effects; buffer-ring-based all-digital on-chip monitor; circuit simulation; fixed logic level; process variability; pulse counter; ring oscillator; Aging; Circuit simulation; Counting circuits; Delay; Logic circuits; Logic devices; MOS devices; Monitoring; Pulse circuits; Ring oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location
Vienna
Print_ISBN
978-1-4244-6612-2
Type
conf
DOI
10.1109/DDECS.2010.5491792
Filename
5491792
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