DocumentCode :
2742823
Title :
Avoiding the WCET Overestimation on LRU Instruction Cache
Author :
Aparicio, L.C. ; Segarra, Josep ; Rodriguez, Claudia ; Villarroel, Jose Luis ; Vials, V.
Author_Institution :
DIIS, Univ. de Zaragoza, Zaragoza
fYear :
2008
fDate :
25-27 Aug. 2008
Firstpage :
393
Lastpage :
398
Abstract :
The WCET computation is one of the main challenges in hard real-time systems, since all further analysis is based on this value. The complexity of this problem leads existing analysis methods to compute WCET bounds instead of the exact WCET. In this work we propose a technique to compute the exact instruction fetch contribution to the WCET (IFC-WCET) in presence of a LRU instruction cache. We prove that an exact computation does not need to analyze the full exponential number of possible execution paths, but only a bounded subset of them. In the benchmark codes we have studied, the IFC-WCET is up to 62% lower than a bound computed with a widely used approach, and the difference between the number of possible execution paths and the ones relevant for the analysis is extremely large.
Keywords :
cache storage; instruction sets; real-time systems; IFC-WCET; LRU instruction cache; WCET computation; WCET overestimation; benchmark codes; instruction fetch contribution; real-time systems; Computer aided instruction; Computer applications; Delay; Embedded computing; Energy consumption; Explosions; Hardware; Pipeline processing; Real time systems; Uncertainty; WCET; cache; real-time;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded and Real-Time Computing Systems and Applications, 2008. RTCSA '08. 14th IEEE International Conference on
Conference_Location :
Kaohsiung
ISSN :
1533-2306
Print_ISBN :
978-0-7695-3349-0
Type :
conf
DOI :
10.1109/RTCSA.2008.10
Filename :
4617309
Link To Document :
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