A VLSI architecture for a dedicated back-propagation simulator

Author

Hirose, Y. ; Anbutsu, H. ; Yamashita, Katsumi ; Goto, Gensuke

Author_Institution

Fujitsu Labs. Ltd., Atsugi

fYear

1991

fDate

8-14 Jul 1991

Abstract

Summary form only given, as follows. A VLSI architecture for a fully dedicated backpropagation algorithm processor is discussed. This processor contains 4 multipliers and 4 ALU´s (arithmetic and logic units) which can work in parallel. The connections of these functional units change according to the current stage of the backpropagation algorithm. The data format is 24-bit floating point (allowing for integers up to 18E6) with an estimated performance of 20 million connection updates per second (MCUPS) at 40 MHz operation. By using several processors and a ring network architecture, it can be enhanced up to 90 MCUPS

Keywords

VLSI; computer architecture; digital arithmetic; learning systems; virtual machines; 24 bit; 40 MHz; ALU; VLSI architecture; backpropagation algorithm processor; data format; floating point arithmetic; multipliers; performance; ring network architecture; simulator; Computer languages; Convolution; Image converters; Image processing; Kernel; Laboratories; Neural networks; Shift registers; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-0164-1

Type

conf

DOI

10.1109/IJCNN.1991.155580

Filename

155580