Test width compression for built-in self testing

Author

Chakrabarty, Krishnendu ; Murray, Brian T. ; Liu, Jian ; Zhu, Minyao

Author_Institution

Dept. of Electr. Comput. Eng., Boston Univ., MA, USA

fYear

1997

fDate

1-6 Nov 1997

Firstpage

328

Lastpage

337

Abstract

We present a method for designing test generator circuits (TGCs) that incorporate a precomputed test set to in the patterns they produce. Our method uses width compression based on the property of d-compatibles, which allows us to encode to more efficiently than previous methods that use only compatibles and inverse compatibles. The TGC consists of a counter, which generates a set of encoded test patterns, and a decompression circuit consisting of simple binary decoders that generate a final sequence containing T_D. These TGCs are applicable to embedded-core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results for the ISCAS 85 and ISCAS CAS 89 benchmark circuits

Keywords

automatic testing; built-in self test; circuit CAD; data compression; integrated circuit testing; integrated logic circuits; logic testing; ISCAS 85 benchmark circuit; ISCAS CAS 89 benchmark circuits; binary decoders; built-in self testing; d-compatibles; decompression circuit; embedded-core circuits; encoded test patterns; inverse compatibles; precomputed test set; test generator circuits; test width compression; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Design methodology; Flip-flops; Logic testing; Research and development; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1997. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-4209-7

Type

conf

DOI

10.1109/TEST.1997.639634

Filename

639634