A 65nm embedded low power SRAM compiler

A highly flexible design methodology of Static Random Access Memory (SRAM) compiler platform is proposed in this paper. With this method, a 65nm CMOS embedded low power single-port SRAM compiler which can generate the whole SRAM IP module files has been developed. A reconfigurable semiautomatic design flow of compiler is obtained, which can be fit for any regular circuits and be more self-adaptive to the migration of technology nodes. According to the design flow, a dual-port SRAM compiler is produced in 65nm process.