Title :
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems
Author :
Leong, C. ; Machado, P. ; Bexiga, V. ; Teixeira, J.P. ; Teixeira, I.C. ; Silva, J.C. ; Lousa, P. ; Varela, J.
Abstract :
The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication channel(s) is (are) faulty. This is not trivial in GALS systems, for which the CDC issue is challenging. The underlying principle of the proposed methodology is to embed a CDC test and diagnosis (CDC T&D) structure in each locally synchronous domain. Complete device-to-device communication channels are tested, including transceivers, buses, and board connectors. Identical test patterns (generated to detect static (stuck-at, shorts and open faults) and dynamic (crosstalk) faults) are used in each FPGA. The proposed CDC T&D methodology is validated in a case study, the acquisition electronics of a complex multi-board, multibus, multi-FPGA (nine Xilinx™ xc2v4000-4bf957) system. Test and validation results are presented.
Keywords :
asynchronous circuits; built-in self test; logic testing; maintenance engineering; telecommunication channels; transceivers; CDC test; FPGA; GALS systems; acquisition electronics; at-speed test; board connectors; built-in clock domain crossing test; buses; crosstalk faults; device-to-device communication channels; diagnosis methodology; globally asynchronous, locally synchronous systems; high resolution diagnosis; identical test patterns; locally synchronous domain; maintenance; prototype validation; repair costs; transceivers; Clocks; Communication channels; Costs; Design methodology; Fault diagnosis; Life testing; Production; Prototypes; System testing; Transceivers; CDC (Clock Domain Crossing) Test and Diagnosis; GALS; Synchronism;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location :
Vienna
Print_ISBN :
978-1-4244-6612-2
DOI :
10.1109/DDECS.2010.5491815
