Hierarchical compiled event-driven logic simulation

A logic simulator is described that includes incremental preprocessing and reduced execution time. The simulator uses compiled code techniques with an event-driven algorithm. Each wire is compiled into a routine that performs fanout processing for that wire, and each gate is compiled into a routine that simulates that gate. At simulation time, the addresses of routines for active nodes and active gates are dynamically compiled into a threaded code sequence for simulating the active parts of the circuits. Gate-level simulation using C code output is up to 7 times faster, using as few as 40 machine instructions per gate event, while machine code would permit 20 instructions per gate event. This technique is then extended to hierarchical simulation, in which a fanout procedure and a simulation procedure are generated for each unique subcircuit type. Hierarchical simulation reduces preprocessing time by allowing incremental recompilation, in which only modified subcircuits are recompiled. The performance improvement is smaller due to the overhead of passing logic values and activation information between subcircuits, but a speed increase of 2 to 4 is realized.<>