An 8.5-ns 112-bit transmission gate adder with a conflict-free bypass circuit

In this paper, we describe a 112-bit transmission gate adder utilizing a new bypass circuit control scheme to improve performance. The estimated propagation delay time is 8.5 ns and the number of transistors is 6,941, both of which are smaller than those of conventional carry select adders (CSA). The adder is integrated in an area of 0.41 x 3.36 mm/sup 2/ with a density of 5,476 transistors/mm2 achieved by 0. 8-/spl mu/m CMOS technology.