Critical path issue in VLSI design

An approach is proposed to the prediction, prior to layout, of the paths and nets that will most likely be critical after layout. The approach makes use of the notion of categorization. The parameters that are highly correlated with the total path delay are first identified. These parameters are combined in a single score function. This function is evaluated for each enumerated path. The k paths with the smallest scores (or largest depending on the score function) are the most critical paths. The nets covered by the selected paths are the predicted critical nets. The nets are also ranked according to their coverage frequencies, timing (load factors), and physical characteristics (number of loading pins). A description is given of the delay model used and the authors´ approach to the prediction of the dangerous paths and nets. Some experimental results are presented.<>