On the mitigation of SET broadening effects in integrated circuits

Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event Transient (SET) pulses that may be generated and propagated through the combinational logic, leading to misbehaviors. SETs are mainly generated by high-energy particles that strikes the circuit near a junction, resulting in a significant charge injection/depletion process, that may produce spurious pulses. These can propagate and change their shape traversing the combinational logic paths, sometimes being broadened and amplified sometimes being filtered. In this paper, we present a place and route algorithm for integrated circuit design, which is able to mitigate and filter the erroneous effects of SETs. The proposed solution has been experimentally evaluated by means of electrical pulse injection within logic resources of several benchmark Integrated Circuits (ICs) implemented in a Flash-based FPGA and by accurate timing analyses. Preliminary results confirm the mitigation of SET broadening effects by acting on physical place and route constraints. On the selected benchmark circuit the algorithm decreases the SET sensitiveness more than 70% with respect to not hardened circuits. Besides, the solution does not introduce any area overhead or delay penalties.