Title :
A layout defect-sensitivity extractor
Author :
de Gyvez, J.P. ; Jess, J.A.G.
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
Abstract :
A method based on a deterministic geometrical construction of critical areas is presented for determining the sensitivity of layouts to spot defects. The models for fatal faults considered are bridges and cuts related to patterns in one layer. The approach, based on the concept of susceptible sites, has a complexity O(N log N), where N is the number of line segments. Only two scans are necessary to extract all susceptible sites, which then are used to compute the critical areas for a whole set of points in a domain of defect size.<>
Keywords :
circuit layout CAD; computational complexity; integrated circuit testing; sensitivity analysis; bridges; complexity; critical areas; cuts; deterministic geometrical construction; fatal faults; layout defect-sensitivity extractor; spot defects; susceptible sites; Analytical models; Bridges; Computational modeling; Manufacturing; Monte Carlo methods; Shape;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.77008
