DocumentCode :
274335
Title :
Fast two-level logic minimizers for multi-level logic synthesis
Author :
Savoj, H. ; Malik, A.A. ; Brayton, R.K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear :
1989
fDate :
5-9 Nov. 1989
Firstpage :
544
Lastpage :
547
Abstract :
Two methods for two-level logic minimization tuned to a multilevel network environment are discussed. Each produces results superior to ESPRESSO. The tautology-based method is very simple and can be coded in less than 700 lines of C language using the existing data structures, and some routines in ESPRESSO. The reduced offset modification is somewhat more complicated but gives the best results. This algorithm has been incorporated into MISII. The authors have demonstrated that a simple filter applied to the don´t care set in this application can be extremely effective.<>
Keywords :
logic CAD; many-valued logics; minimisation of switching nets; ESPRESSO; MISII; data structures; don´t care base minimisation; don´t care set; multi-level logic synthesis; multilevel network environment; reduced offset modification; tautology-based method; two-level logic minimization; two-level logic minimizers; Birth disorders; Contracts; Filters; Logic; Petroleum; Radio access networks; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
Type :
conf
DOI :
10.1109/ICCAD.1989.77009
Filename :
77009
Link To Document :
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