New ATPG techniques for logic optimization

Algorithms are presented for RI (redundancy identification) and RR (redundancy removal). With fault simulation and a backtrack limit of 10, the RI program is able to find a test for all testable faults and identify all the redundant faults in each of the ISCAS benchmark examples. The RR program makes the whole benchmark set 100% testable for single stuck-at faults, and generates the test, in less than 1 CPU hour (SUN4/280). The algorithms were developed for equivalence-based logic optimization applications, which accentuate the role of heuristics in the process of automatic test program generation (ATPG), since this diminishes the role of fault simulation. The authors compare a limited set of results obtained by RR to those of existing logic optimization programs. The results show that in most cases, superior results can be obtained with factors of tens to hundreds speedup in CPU time.<>