DocumentCode :
274338
Title :
Multi-level logic optimization using binary decision diagrams
Author :
Matsunaga, Y. ; Fujita, M.
Author_Institution :
Fujitsu Lab. Ltd., Kawasaki, Japan
fYear :
1989
fDate :
5-9 Nov. 1989
Firstpage :
556
Lastpage :
559
Abstract :
A multilevel logic optimizer, which is based on the transduction method, is introduced. The original transduction method is good for optimization, but its calculation time and storage area increase exponentially with the number of inputs because of the use of truth tables. To save CPU time and memory space, the authors implemented this algorithm using ordered binary decision diagrams (OBDD) as the data structure for representing logic functions. Since OBDD does not become as large as other representations, it can handle large circuits without partitioning.<>
Keywords :
logic CAD; many-valued logics; minimisation of switching nets; binary decision diagrams; large circuits; logic functions; multilevel logic optimizer; storage area; transduction method; Artificial intelligence; Boolean functions; Central Processing Unit; Data structures; Input variables; Laboratories; Logic circuits; Logic functions; Optimization methods; Partitioning algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
Type :
conf
DOI :
10.1109/ICCAD.1989.77012
Filename :
77012
Link To Document :
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