Advanced embedded memory testing: Reducing the defect per million level at lower test cost

Summary form only given: Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of device-parameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality. The objective of this embedded tutorial is to provide test engineers, memory and ASIC designers, researchers, students and managers with an overview of state-of-the art of fault models for SRAMs (including traditional fault modeling and recent development in fault models for current and future technologies), together with the latest test algorithms. Next, it describes test plans, which are shown to depend on the size of the SRAM, its speed, and the application domain. Thereafter, industrial results are used to show the effectiveness of the proposed algorithms and stresses. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.