Title :
14/spl mu/A Data Retention DRAM with Intermittent Bit-Line Balancing Scheme
Author :
Tamaki, S. ; Shimizu, T. ; Tokushige, K. ; Mizukami, T. ; Sato, Y. ; Tajima, J.
Author_Institution :
NEC Corporation
fDate :
May 30 1991-June 1 1991
Keywords :
Clocks; Counting circuits; Data engineering; Energy consumption; Equalizers; Large scale integration; Power dissipation; Pulse amplifiers; Random access memory; Signal generators;
Conference_Titel :
VLSI Circuits, 1991. Digest of Technical Papers. 1991 Symposium on
Conference_Location :
Oiso, Japan
DOI :
10.1109/VLSIC.1991.760112
