DocumentCode
2743479
Title
Asynchronous design, Quo Vadis?
Author
Yakovlev, Alex
Author_Institution
Newcastle Univ., Newcastle upon Tyne, UK
fYear
2010
fDate
14-16 April 2010
Firstpage
3
Lastpage
3
Abstract
This talk will briefly discuss the history of the asynchronous design methodology, as its principles and approaches have evolved through the various notions of circuits and systems operating without a global clock, i.e., asynchronous FSMs, speed-independent and delay-insensitive circuits, self-timed systems, multi-synchronous and GALS SOCs. Along the way, and focusing more on the present day hiatus, opportunities, success stories and problems will be discussed as they are being faced in academic research and industrial exploitation. The speaker will be happy to share his experiences of near thirty years in the research he has been involved in the area of self-timed systems and circuits. These will cover designing systems with multiple clock domains, various signalling schemes and protocols, self-timed circuit synthesis, verification, Petri nets, timing-elastic and power-adaptive systems. Should he be particularly adventurous on the day, he might even try to make some predictions into future developments.
Keywords
Petri nets; asynchronous circuits; logic design; system-on-chip; GALS SOC; Petri nets; asynchronous FSM; asynchronous design methodology; circuit verification; delay-insensitive circuit; multiple clock domains; power-adaptive system; self-timed circuit synthesis; signalling scheme; speed-independent circuit; timing-elastic system; Circuits and systems; Clocks; Concurrent computing; Delay systems; Design methodology; History; Petri nets; Protocols; Signal design; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location
Vienna
Print_ISBN
978-1-4244-6612-2
Type
conf
DOI
10.1109/DDECS.2010.5491832
Filename
5491832
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