• DocumentCode
    2744371
  • Title

    Testability features of AMD-K6TM microprocessor

  • Author

    Fetherston, R. Scott ; Shaik, Imtiaz P. ; Ma, Siyad C.

  • Author_Institution
    California Microprocessor Div., Adv. Micro Devices Inc., Sunnyvale, CA, USA
  • fYear
    1997
  • fDate
    1-6 Nov 1997
  • Firstpage
    406
  • Lastpage
    413
  • Abstract
    This paper describes the testability features and test pattern development methodologies for the AMD-K6TM microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests
  • Keywords
    built-in self test; cache storage; computer testing; design for testability; electric current measurement; logic testing; microprocessor chips; production testing; read-only storage; reduced instruction set computing; AMD-K6TM microprocessor; BIST; DFT; IDDQ test; RISC; ROM; cache memory array; embedded design; manufacturing tests; path delay fault; scan test pattern; static timing analysis; stuck-at test; testability; Built-in self-test; Decoding; Delay; Design for testability; Libraries; Microprocessors; Read only memory; Reduced instruction set computing; Test pattern generators; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1997. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-4209-7
  • Type

    conf

  • DOI
    10.1109/TEST.1997.639643
  • Filename
    639643
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2744371