A Synthesis Technique for Reducing Leakage Based on Signal Controllability

Leakage is becoming a dominant factor in the total power consumption of a logic circuit. Most of the methods presented in the literature are based on adding a sleep input to the circuit that allow an external controller to turn the circuit off when it is not switching. Limited work has been done in designing external controllers for local low power sleep control. In this paper, we propose a novel transistor level synthesis flow for reducing the leakage power of static CMOS circuits. We first present a sleep based leakage reduction method for standard library cells. Then, we perform simultaneous gate replacement and sleep signal assignment based on the controllability chains of circuit signals. With this synthesis flow, no external controller is required for driving the sleep signals of a circuit. Experiments were conducted on different circuits with 0.18 mum technology, and the new circuits consumed an average of 10 times less leakage than the initial circuit