Rain Current Variation Caused By Grain Boundaries In Polysilicon TFTs

The drain current (id) ofpolysilicon TFTs ( thin film transistors) is studied as a function of drain voltage (Vd). A large variation of Id (as large as 100% at Vd=10V) is observed when the grain size (~1/spl mu/m) of the polysilicon is comparable to the device size. The drain current increases for a TFT with a grain boundary in the channel region near the drain edge. This increase in Id results from an enhancement of the impact ionization due to a high electric field at the grain boundary. This is verified with a two-dimensional simulator where the grain boundary is treated as an array of midgap states.