On-line testable logic design for FPGA implementation

In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of faults within a FPGA. This is accomplished by utilizing a unique set of cells to implement a design. These cells operate on the premise of a two-rail checker, thus producing both the normal and complemented output when a cell is operating correctly, and two outputs of the same value in the presence of a fault. Faults generated in an intermediate cell is propagated to the final outputs, thus allowing on-line testability of a FPGA-based logic system