A 2.3/spl mu/m/sup 2/, Single-Bit-Line SRAM Cell with High Soft-Error-Immune Structure
Author :
Yamanaka, T. ; Ueda, K. ; Ohki, N. ; Hashimoto, N. ; Hashimoto, T. ; Shimizu, A. ; Ishida, H. ; Nishida, T. ; Kure, T. ; Takasugi, K. ; Sasaki, K. ; Takeda, E. ; Nagano, T.
Author_Institution :
Hitachi, Ltd.
fYear :
1993
fDate :
17-19 May 1993
Firstpage :
71
Lastpage :
72
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on
