Title :
R-2 Global Planarization (Flow vs. CMP)
Author :
Tsukamoto, K. ; Pintchovski, F.
Author_Institution :
Mitsubishi
Abstract :
Summary form only given. Multilevel metallization has become one of the most challenging modules in advanced - 0.5 ,um and beyond - semiconductor processing. A key technology within the metallization module is the planarization of interlevel dielectrics. The demand for increased planarization has been increasing with each `shrink¿ generation and is basically lithography driven.
Keywords :
Semiconductor device manufacturing;
Conference_Titel :
VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIT.1993.760274
