On modeling and simulating chip design processes: The RS model

The International Technology Roadmap for Semiconductors (ITRS) reports about the increasing divergence between what technological advances afford (in terms of the number of transistors on a single chip) and the capability to design these complex chips: the ldquoDesign Gaprdquo. The chip design industry evolved into very sophisticated and complex processes needing managerial approaches to master them. Missing possibilities to evaluate course and outcome of projects in a simulative way entail soaring losses. In this paper, we present a pioneer approach that allows for modeling design processes in a formal manner. A prototype implementation of a simulator based on our model attests the appropriateness of the model.