Deep Sub-Micron CMOS (/spl mu/m CMOS: RT or Cryo-, 0.25/spl mu/m pMOS: Buried or Surface Channel?)

Summary form only given. Scaling MOS devices has provided high performance, high density CMOS LSIs, such as memories and microprocessors, and scaling remains the key to obtaining better performance in the future. This session will examine deep sub-micron CMOS technologies from the point of view of device design, process technology, circuit performance, reliability and integratability.