DocumentCode :
2746454
Title :
Optimizing translation out of SSA using renaming constraints
Author :
Rastello, F. ; De Ferriére, F. ; Guillon, C.
Author_Institution :
LIP, Ecole Normale Superieure de Lyon, France
fYear :
2004
fDate :
20-24 March 2004
Firstpage :
265
Lastpage :
276
Abstract :
Static Single Assignment form is an intermediate representation that uses Φ instructions to merge values at each confluent point of the control flow graph. Φ instructions are not machine instructions and must be renamed back to move instructions when translating out of SSA form. Without a coalescing algorithm, the out of SSA translation generates many move instructions. Leung and George [A. L. Leung et al., (1999)] use a SSA form for programs represented as native machine instructions, including the use of machine dedicated registers. For this purpose, they handle renaming constraints thanks to a pinning mechanism. Pinning Φ arguments and their corresponding definition to a common resource is also a very attractive technique for coalescing variables. Extending this idea, we propose a method to reduce the Φ-related copies during the out of SSA translation, thanks to a pinning-based coalescing algorithm that is aware of renaming constraints. We implemented our algorithm in the STMicroelectronics Linear Assembly Optimizer [B. Dupont de Dinechin et al., (2000)]. Our experiments show interesting results when comparing to the existing approaches of Leung and George [A. L. Leung et al., (1999)], Sreedhar et al. [V. Sreedhar et al., (1999)], and Appel and George for register coalescing [L. George et al., (1996)].
Keywords :
assembly language; constraint handling; flow graphs; instruction sets; optimising compilers; program interpreters; Φ instructions; STMicroelectronics Linear Assembly Optimizer; Static Single Assignment form; control flow graph; machine dedicated registers; native machine instructions; pinning-based coalescing algorithm; renaming constraint handling; translation optimization; Assembly; Constraint optimization; Digital signal processing; Flow graphs; Hardware; Induction generators; Joining processes; Pipeline processing; Processor scheduling; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Code Generation and Optimization, 2004. CGO 2004. International Symposium on
Print_ISBN :
0-7695-2102-9
Type :
conf
DOI :
10.1109/CGO.2004.1281680
Filename :
1281680
Link To Document :
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