Interconnect reliability modeling for lead-free fan-out chip scale package

The fan-out-type chip scale package (fan-out CSP) is an embedded chip packaging technology that eliminates the need for wirebonds and flip-chip bumps. In this study, the board-level reliability of fan-out CSP is studied by using three-dimensional finite element analysis. A design of simulations study is applied to investigate the influences of package geometry on the board-level interconnect reliability of fan-out CSP. Results of the analysis indicate that better board-level reliability for the fan-out CSP can be achieved by using a thicker die with thinner molding compound. In addition, the response surface model obtained from the design of simulations study can be served as the basis for further fan-out CSP design optimization.