The high frequency parasitic effect characterization of packages with test chip inside

An RLC meter was used to measure the inductances and capacitances of both plastic quad flat package (PQFP) and plastic ball grid array (PBGA) with test chips inside the packages. A test chip was used to simulate the real package condition, although the standard measurement guideline such as EIA/JED123 does not include it. Combining test chip layout, test ground fixture and grounding technique, the complex n-lead model could be simplified into a one-lead model which leads to obtain the inductance or capacitance of pins in a package easily. Two kinds of packages PQFP and PBGA were investigated, each one had five samples which were measured from 0 to 3 GHz range. From the inductance/ capacitance versus frequency curves, the frequency limitation of packages is obtained. The average inductance values per mm for both PQFP and PBGA are 0.99plusmn0.05 nH/mm and 0.95plusmn0.05 nH/mm, respectively, while the average capacitance values for PQFP and PBGA are 0.89plusmn0.02 pF and 0.79plusmn0.02 pF as relating to each.