High-speed CRC computations using improved state-space transformations

Previously, a state-space similarity transform was proposed to reduce the feedback loop complexity of a parallel Cyclic Redundancy Check architecture and enable retiming. This paper investigates the open research question concerning the impact of varying the vector used to construct the transformation matrix. We perform exhaustive searches of the vector space for frequently referenced generator polynomials when the input size is equal to the degree of the generator polynomial. The set of vectors which yield minimal hardware state-space representations is obtained. Then, application-specific integrated circuit (ASIC) experiments are performed. The ASIC implementation results for the minimized state spaces demonstrate improvement in both area and timing as compared to the original ones. Finally, it is concluded that the vectors obtained for a fixed generator polynomial are also good choices for other input sizes.