A low-cost S-box for the Advanced Encryption Standard using normal basis

The advanced encryption standard (AES) is a newly accepted secret key cryptographic standard for secure transfer of blocks of data. Among different transformations, the SubBytes transformation is the most expensive one in terms of the chip area and the power consumption in the hardware implementation of the AES. It consists of 16 S-boxes and hence the hardware optimization of the S-box is critical to reach a low-cost AES. In this paper, we present a low-cost S-box for the AES. Instead of using look-up tables for implementing the S-box, logic gate implementation based on a previously known low-complexity composite field using normal basis is utilized. Then, we present improved formulations for the inversion in the sub-fields within the S-box to reduce the area complexity of the implementations. After analyzing the complexities of the new architecture, we compare the ASIC implementation of the proposed S-box using 0:18mu CMOS technology with the previous ones. It is shown that the presented scheme has the lowest power consumption and area compared to its counterparts available in the open literature.