RUBASTEM: a method for testing VHDL behavioral models

Author

Andrews, Anneliese ; O´Fallon, Andrew ; Chen, Tom

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

fYear

2004

fDate

25-26 March 2004

Firstpage

187

Lastpage

196

Abstract

Verification of high-assurance system designs before they are fabricated on chips reduces time and money costs related to chip testing. Test benches, which are used in simulating and verifying VHDL designs, need to perform efficiently and effectively. Test automation through the automated generation of test patterns increases the efficiency and effectiveness of behavioral verification. We apply heuristic rules to generate test cases for VHDL behavioral designs. Their aim is to increase code coverage. They are based on control-flow and data-flow analysis. We applied the RUle-BAsed Software TEsting Method (RUBASTEM) to small, medium, and large examples. The results of RUBASTEM showed that this method achieves higher branch coverage.

Keywords

data flow analysis; hardware description languages; knowledge based systems; logic CAD; logic testing; program testing; program verification; RUBASTEM; VHDL behavioral models; VHSIC; Very High Speed Integrated Circuit; automated test pattern generation; data flow analysis; hardware description language; hardware verification; rule-based software testing method; Automatic control; Automatic test pattern generation; Automatic testing; Automation; Costs; Data analysis; Performance evaluation; System testing; System-on-a-chip; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

High Assurance Systems Engineering, 2004. Proceedings. Eighth IEEE International Symposium on

ISSN

1530-2059

Print_ISBN

0-7695-2094-4

Type

conf

DOI

10.1109/HASE.2004.1281743

Filename

1281743