Mixed-signal CVNS adder for two-operand binary addition

The continuous valued number system (CVNS) has been used to implement a 16-bit mixed-signal adder for performing two-operand binary additions. The adder takes advantage of higher speed of operation of analog signal processing units, while digital blocks have been used at the output of the adder to provide better driving capability by inserting buffers. The analog circuits, process and determine the existence of carry signal on a group of binary inputs. Moreover, analog signals are used for addition over a group of binary digits, using current mode circuitry, to reduce the area and increase the speed of operations. In this paper, design of a mixed signal CVNS adder is proposed, which is used for two operand binary addition. The CVNS radix is chosen low, equal to 2, to reduce the complexity of conversion circuits between the binary and CVNS system.