System-level memory modeling for bus-based memory architecture exploration

System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we propose a novel system-level approach to memory design, which was not yet well addressed in existing SLD methodologies. In particular, we extend the SpecC methodology by defining various memory models at different levels of abstraction and a set of refinement rules that support fast and accurate memory architecture exploration. We demonstrate the experimental results using a case study in which we show the benefit of our approach.