High performance signed-digit decimal adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with the revision of the IEEE 754 standard. This paper presents a new scheme for carry-free decimal addition using a signed-digit representation. In order to simplify the hardware requirements, each signed decimal digit uses a two´s complement representation instead of complex representations found in other signed-digit decimal arithmetic implementations. Flagged adder speculation is used for fast addition of the constants required in the correction step. The proposed scheme is compared to existing signed-digit decimal adders. Each architecture is synthesized on 0.18 mum technology for comparison in area, delay and power. The results show that both operation speed and area usage can be significantly improved with respect to existing signed-digit decimal adders.