DocumentCode :
2747828
Title :
To DFT or not to DFT?
Author :
Wei, S. ; Nag, P.K. ; Blanton, R.D. ; Gattiker, A. ; Maly, W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
1997
fDate :
1-6 Nov 1997
Firstpage :
557
Lastpage :
566
Abstract :
Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first step of this study involved development of a new DFT cost/benefit trade-off modeling procedure. Next, the developed cost model (which we call the CMU Test Cost model) was used, with a range of parameters representing typical industrial conditions, to answer the question: to DFT or not to DFT. The obtained results indicate that in the DFT application space there exist regions in which one can provide a clear answer to this question. There also exist regions of uncertainty. One of the objectives of our study has been to identify ways of minimizing this uncertain region
Keywords :
cost-benefit analysis; design for testability; integrated circuit modelling; integrated circuit testing; integrated circuit yield; CMU test cost model; DFT; application space; cost/benefit trade-off modeling procedure; decision-making process; design-for-testability cost modeling; industrial conditions; uncertain region; Circuit testing; Controllability; Costs; Design for testability; Hardware; Life testing; Power engineering and energy; Probes; System testing; Uncertainty;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-4209-7
Type :
conf
DOI :
10.1109/TEST.1997.639664
Filename :
639664
Link To Document :
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