Synthesis of two-level dynamic CMOS circuits

CMOS circuits are presently used for the realization of VLSI circuits because of low power consumption and high integration density. But, because of the use of both n-block and D-block, static full complementary CMOS circuits are not area efficient. The problem is overcome in dynamic circuits using either a p-block or a n-block in the realization of digital circuits. However, cascading of dynamic circuits leads to the serious problem of clock skew. To overcome this problem, domino and NORA techniques have been proposed. This paper proposes a novel approach for the synthesis of two-level dynamic circuits with the minimum number of gates and with an optimized number of transistors using domino and NORA techniques. The NORA implementation is completely inverter-free. The approach is based on a novel concept called unate decomposition, which decomposes any given Boolean function in terms of unate functions allowing seamless realization using dynamic CMOS gates