Design of the integrated parallel processing unit IPU with systolic VLSI chips

Author

Chen, Wen-Tsuen ; Wang, Jia-Shung ; Huang, Shing-Tsaan ; Yang, Shi-Nine ; Chang, Long-Wen ; Horng, Shi-Jinn ; Liu, Chia-Cheng ; Yang, Chang-Biau ; Huang, Ruey-Zone ; Liaw, Bern-Chern

Author_Institution

Inst. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

1989

fDate

17-19 May 1989

Firstpage

276

Lastpage

280

Abstract

The design of a massively parallel processing system IPU (integrated parallel processing unit) is described. It is a two-dimensional mesh-connected parallel processing array operated in SIMD (single instruction, multiple data) fashion and attached to a host computer. The IPU array is implemented with 64 systolic VLSI (very-large-scale integration) chips each of which consists of four processing elements. A hardware interface that acts as a bridge between host computer and the IPU array has also been designed. A high-level programming language environment for designing the parallel program to run on this array is provided. Several applications are discussed. Some experimental results on the execution speed of the IPU system are reported

Keywords

VLSI; cellular arrays; parallel processing; programming environments; IPU; SIMD; VLSI; hardware interface; high-level programming language environment; integrated parallel processing unit; processing elements; systolic VLSI chips; two-dimensional mesh-connected parallel processing array; Computer interfaces; Computer science; Concurrent computing; Control systems; Hardware; Multiprocessing systems; Parallel processing; Parallel programming; Process design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68629

Filename

68629