The recursive grid layout scheme for VLSI layout of hierarchical networks

We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchical networks. In particular we construct optimal VLSI layouts for butterfly networks, generalized hypercubes, and star graphs that have areas within a factor of 1+o(1) from their lower bounds. We also derive efficient layouts for a number of other important networks, such as cube-connected cycles (CCC) and hypernets, which are the best results reported for these networks thus far