DocumentCode :
2748601
Title :
Cache management in a tightly coupled fault tolerant multiprocessor
Author :
Banatre, M. ; Joubert, P.
Author_Institution :
IRISA-INRIA, Beaulieu Univ., Rennes, France
fYear :
1990
fDate :
26-28 June 1990
Firstpage :
89
Lastpage :
96
Abstract :
Some aspects of a fault-tolerant tightly coupled multiprocessor architecture are presented. The originality of this architecture resides in the use of a stable transactional memory shared by all processors. To ensure fault tolerance, each update of a memory block is included into an atomic transaction managed by the stable transactional memory. All the blocks that are part of a transaction are written back atomically into stable transaction memory. This work focuses on a protocol which ensures the atomic update of blocks into stable transactional memory when they have been modified by several caches. The results of various simulations that were conducted in order to evaluate the potential performance of the proposed architecture are also presented.<>
Keywords :
buffer storage; computer architecture; fault tolerant computing; multiprocessing systems; atomic transaction; multiprocessor architecture; protocol; simulations; stable transactional memory; tightly coupled fault tolerant multiprocessor; Cache storage; Computational modeling; Computer architecture; Fault tolerance; Hardware; Iris; Memory management; Performance evaluation; Proposals; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1990. FTCS-20. Digest of Papers., 20th International Symposium
Conference_Location :
Newcastle Upon Tyne, UK
Print_ISBN :
0-8186-2051-X
Type :
conf
DOI :
10.1109/FTCS.1990.89339
Filename :
89339
Link To Document :
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