Identifying rate mismatch through architecture transformation

Rate mismatches are often missed when simulation is used as a validation tool for embedded systems because it is hard to determine if the mismatch was introduced by the coupling of the software models, the communication protocol, a flawed system design or a combination of the three factors. By eliminating the ambiguity introduced by the software model couplings and the communication protocol, it is possible to trace rate mismatches to flawed system design. The High Level Architecture details the couplings between the various components present in the system, while the Time Triggered Protocol provides deterministic, reliable and fault-tolerant communication between the components. This paper presents an mapping of the High Level Architecture specification of the system to the Time Triggered Protocol. Any rate mismatches detected, can then be attributed to flawed system design, making simulation a powerful validation tool for the design and implementation of hard real-time embedded systems.