Abstract :
A high performance ATM switch architecture, named Gauss, has been proposed. Using traffic observations and known design principles a number of favourable properties have been obtained. Due to a fully interconnected architecture the Gauss ASE (ATM switching element) is nonblocking and can be used for multi and broadcast traffic. Due to its modularity the Gauss ASE can grow towards a large single-stage output buffered switch fabric that can offer low delays and low delay jitter and which is probably easier to manage. The suitability for VLSI has been shown; only two types of integrated circuits are needed. Inputs are allowed to operate asynchronously and, if necessary, loss priority can also be handled. The Gauss ASE can be made fault tolerant by providing spare inputs and outputs
