DocumentCode
274973
Title
WASP: a demonstrated wafer scale technology
Author
Jalowiecki, Ian P. ; Hedge, Stephen J. ; Lea, R.M.
Author_Institution
Brunel Univ., Uxbridge, UK
fYear
1990
fDate
19-22 Mar 1990
Firstpage
184
Lastpage
189
Abstract
The authors review WASP 1 and discuss the WASP 2a and WASP 2b wafer scale integration (WSI) massively parallel processor technology demonstrators, implemented in standard CMOS technology. These latter devices are defect-tolerant arrays of 864 and 6480 processing elements and integrate 1.26 M transistors (4 cm×4 cm) and 8.43 M transistors (10 cm×10 cm). The two variants (WASP 2a and WASP 2b) are examples of the associative string processor (ASP) architecture, developed by Brunel University. WASP 2a/2b, as well as their successful predecessor, WASP 1, are the technology demonstrators of the UK Alvey WSI programme
Keywords
CMOS integrated circuits; VLSI; fault tolerant computing; parallel architectures; parallel machines; ASP architecture; UK Alvey WSI programme; WASP 1; WASP 2a; WASP 2b wafer scale integration; WSI; associative string processor; defect-tolerant arrays; massively parallel processor technology demonstrators; processing elements; standard CMOS technology; technology demonstrators; transistors;
fLanguage
English
Publisher
iet
Conference_Titel
UK IT 1990 Conference
Conference_Location
Southampton
Type
conf
Filename
114286
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