Abstract :
Developments in silicon bipolar and GaAlAs/GaAs heterojunction bipolar technologies are reviewed and the performance of the two technologies for high-speed ECL circuits are compared. The gate delays for state-of-the-art circuits are estimated using an analytical equation, which expresses the gate delay as a linear weighted sum of all the time constants in the circuit. A common idealised transistor layout is used in order to eliminate geometry differences from the comparison, and highlight the role of the heterojunction and the fundamental material and device properties. Gate delays of 8.6 and 26.9 ps are predicted for 1 μm GaAlAs/GaAs and silicon bipolar technologies respectively. Scaling the emitter width to 0.4 μm reduces the gate delay for silicon technology to 17.2 ps, but gives only a small improvement to 8.1 ps for GaAlAs/GaAs technology. These results are explained by considering the limiting time constants for the two technologies
Keywords :
III-V semiconductors; bipolar integrated circuits; emitter-coupled logic; gallium arsenide; heterojunction bipolar transistors; integrated logic circuits; silicon; 0.4 to 1 micron; 8.1 to 26.9 ps; GaAlAs-GaAs; Si; analytical equation; common idealised transistor layout; device properties; emitter width; gate delays; heterojunction bipolar technologies; high-speed ECL circuits; linear weighted sum; silicon bipolar technologies; state-of-the-art circuits; time constants;
