Environmental Challenges for 45-nm and 32-nm node CMOS Logic

Author

Boyd, Sarah ; Dornfeld, David ; Krishnan, Nikhil ; Moalem, Mehran

Author_Institution

Univ. of California, Berkeley

fYear

2007

fDate

7-10 May 2007

Firstpage

102

Lastpage

105

Abstract

The objective of this work is to understand the materials and energy requirements, and emissions associated with new semiconductor manufacturing technology nodes. Current and near-future CMOS technologies (for the 45-nm and 32-nm nodes) are investigated using an inventory based on bottom-up process data. The process flow of the CMOS chip is modeled by updating an existing inventory analysis (for 130 nm node devices) to include strained Si channels, metal gates, 10 layers of interconnect and high-k gate dielectrics used in 45-nm and 32-nm CMOS nodes. Conclusions are made concerning emissions of new materials and trends in life cycle energy consumption of logic devices.

Keywords

CMOS logic circuits; environmental factors; high-k dielectric thin films; integrated circuit interconnections; inventory management; semiconductor device manufacture; silicon; CMOS logic; bottom up process data; energy requirements; environmental challenges; interconnect; inventory analysis; semiconductor manufacturing technology; size 130 nm; size 32 nm; size 45 nm; strained Si channel; CMOS logic circuits; CMOS process; CMOS technology; Dielectric materials; Energy consumption; High K dielectric materials; Logic devices; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor materials; Environmental Management; Life Cycle Assessment; Life Cycle Inventory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics & the Environment, Proceedings of the 2007 IEEE International Symposium on

Conference_Location

Orlando, FL

ISSN

1095-2020

Print_ISBN

1-4244-0861-X

Type

conf

DOI

10.1109/ISEE.2007.369375

Filename

4222864