Title :
Design automation based upon a distributed self-timed architecture
Author_Institution :
South Bank Polytech., London, UK
Abstract :
Describes a design automation tool for digital systems, ZP, which incorporates both system level correctness checking of control and data flow and automatic translation to a hardware or software target. It differs from the existing class of silicon compiler tools both in the provision of analytical routines which detect characteristics such as correct termination and freedom from indeterminacy and deadlock in large concurrent systems, and in that the output data is not tied into a particular language or technology, allowing access to a range of implementations
Keywords :
VLSI; circuit CAD; integrated logic circuits; logic CAD; analytical routines; automatic translation; concurrent systems; correct termination; data flow; deadlock; design automation tool; digital systems; distributed self-timed architecture; indeterminacy; silicon compiler tools; system level correctness checking;
Conference_Titel :
UK IT 1990 Conference
Conference_Location :
Southampton
