• DocumentCode
    2750050
  • Title

    Fault-based triangular basis multiplication over GF(2m) using bit-level parity prediction scheme

  • Author

    Jenn-Shyong Homg ; Chiou-Yng Lee ; I-Chang Jou ; Teh-Sheng Huang

  • Author_Institution
    Nat. Kaohsiung First Univ., Tainan
  • fYear
    2007
  • fDate
    Oct. 30 2007-Nov. 2 2007
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Recently, many researchers have proved that cryp- tosystems can be easily broken by the fault based side-channel cryptanalysis. To fight against such fault based side-channel cryptanalysis, a bit-parallel triangular basis systolic multiplier with on-line error detection capability is then presented. The architecture is used by a bit-level parity prediction scheme to detect even-multiple and odd-multiple errors in triangular basis multiplication, and then saves about 77% space complexity as compared to traditional fault-based multipliers.
  • Keywords
    cryptography; error correction; error correction codes; bit-level parity prediction scheme; cryptosystems; fault-based triangular basis multiplication; on-line error detection; side-channel cryptanalysis; systolic multiplier; Arithmetic; Circuit faults; Circuit testing; Cryptography; Error correction codes; Fault detection; Galois fields; Hardware; Polynomials; Telecommunications;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2007 - 2007 IEEE Region 10 Conference
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-1271-6
  • Type

    conf

  • DOI
    10.1109/TENCON.2007.4428772
  • Filename
    4428772