A novel VLSI architecture for full-search variable block-size motion estimation

Variable block-size motion estimation (VBSME) has become an important technique in H.264/AVC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/AVC based on full-search motion estimation algorithm. The proposed architecture reuses the sum of absolute differences (SAD) to reduce the calculation complexity, thus minimizes the number of registers. A new scan order is introduced to produce the distributed SAD outputs, so the number of output buses is reduced. The architecture in this paper has scalability to compute VBSME with variable size of searching windows and PEs. Compared to the conventional approaches, the architecture shows a high throughput rate with less hardware. After logic synthesis using the DonbuAnam 0.18um standard cell library, the number of gate counts is 39K (16 PEs) and the maximum operating clock frequency is 416 MHz (256 fps@CIF).