Novelty of TAH framework in computing reduced wire length two- and three-layer routing solutions

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.