Current status and future trend on CAD tools for VLSI testing

Author

Cheng, Wu-Tung

Author_Institution

Mentor Graphics Corp., Wilsonville, OR, USA

fYear

2000

fDate

2000

Firstpage

10

Lastpage

11

Abstract

For current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are based on scan DFT and automatic test pattern generation (ATPG). However, to reduce the need to use an external tester, and to ease test reuse at the system level, more designs are using BIST to test logic. In the future, with system on chip (SoC) requirements and deep Sub-Micron (DSM) technologies, we believe that BIST and scan-based ATPG will continue to be the main solutions to VLSI testing. However, to be successful, some improvements are needed. The author discusses future trends in three categories: test quality, test application cost and test development effort

Keywords

VLSI; automatic test pattern generation; built-in self test; circuit CAD; integrated circuit design; integrated circuit economics; logic testing; ATPG; BIST; CAD; SoC; VLSI design; VLSI testing; automatic test pattern generation; deep Sub-Micron technologies; embedded memories; scan-based ATPG; system on chip; test application cost; test development; test logic; test quality; Automatic logic units; Automatic test pattern generation; Built-in self-test; Design automation; Design for testability; Logic design; Logic testing; System testing; System-on-a-chip; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893593

Filename

893593